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1. general description the 74lvc74a-q100 is a dual edge triggered d-type flip-flop. it has individual data (nd) inputs, clock (ncp) inputs, set (ns d) and (nr d) inputs, and complementary nq and nq outputs. the set and reset are asynchronous active lo w inputs and operate independently of the clock input. information on the data input is transferred to the nq output on the low-to-high transition of the clock pulse. the nd inputs must be stable one set-up time prior to the low-to-high clock transition, for predictable operation. schmitt trigger action at all inputs makes the circuit highly tolerant of slower input rise and fall times. this product has been qualified to the automotive electronics council (aec) standard q100 (grade 1) and is suitable for use in automotive applications. 2. features and benefits ? automotive product qualif ication in accordance with aec-q100 (grade 1) ? specified from ? 40 ? c to +85 ? c and from ? 40 ? c to +125 ? c ? 5 v tolerant inputs for interlacing with 5 v logic ? wide supply voltage range from 1.2 v to 3.6 v ? cmos low power consumption ? direct interface with ttl levels ? esd protection: ? mil-std-883, method 3015 exceeds 2000 v ? hbm jesd22-a114f exceeds 2000 v ? mm jesd22-a115-a exceeds 200 v (c = 200 pf, r = 0 ? ) ? multiple package options 74lvc74a-q100 dual d-type flip-flop with set and reset; positive-edge trigger rev. 2 ? 5 april 2013 product data sheet
74lvc74a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 5 april 2013 2 of 18 nxp semiconductors 74lvc74a-q100 dual d-type flip-flop with set and reset; positive-edge trigger 3. ordering information 4. functional diagram table 1. ordering information type number package temperature range name description version 74lvc74ad-q100 ? 40 ? c to +125 ? c so14 plastic small outline package; 14 leads; body width 3.9 mm sot108-1 74lvc74apw-q100 ? 40 ? c to +125 ? c tssop14 plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 74LVC74ABQ-Q100 ? 40 ? c to +125 ? c dhvqfn14 plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 ? 3 ? 0.85 mm sot762-1 fig 1. logic symbol fig 2. iec logic symbol fig 3. functional diagram mna418 rd ff sd 410 q 1q 2q 1q 2q 5 9 2 12 3 11 6 8 q 1sd cp 2cp 1cp 2d 1d d 2sd 113 1rd 2rd mna419 6 3 2 c1 4 s 1d 1 r 5 8 11 12 c1 10 s 1d 13 r 9 rd ff sd 4 q 1q 1q 5 2 3 6 q 1sd cp 1cp 1d d 1 1rd mna420 rd ff sd 10 q 2q 2q 9 12 11 8 q 2sd cp 2cp 2d d 13 2rd
74lvc74a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 5 april 2013 3 of 18 nxp semiconductors 74lvc74a-q100 dual d-type flip-flop with set and reset; positive-edge trigger 5. pinning information 5.1 pinning fig 4. logic diagram for one flip-flop mna421 sd cp rd d c c q c c c c c c q c c (1) this is not a supply pin. the substrate is attached to this pad using conductive die atta ch material. there is no electrical or mechanical requi rement to solder this pad. however, if it is soldered, the solder land should remain floating or be connected to gnd. fig 5. pin configuration for so14 and tssop14 fig 6. pin configuration for dhvqfn14

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74lvc74a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 5 april 2013 4 of 18 nxp semiconductors 74lvc74a-q100 dual d-type flip-flop with set and reset; positive-edge trigger 5.2 pin description 6. functional description [1] h = high voltage level; l = low voltage level; x = don?t care [1] h = high voltage level; l = low voltage level; ? = low-to-high transition; q n+1 = state after the next low-to-high cp transition; x = don?t care table 2. pin description symbol pin description 1r d, 2r d 1, 13 asynchronous reset-direct input (active low) 1d, 2d 2, 12 data input 1cp, 2cp 3, 11 clock input (low-to-high, edge-triggered) 1s d, 2s d 4, 10 asynchronous set-di rect input (active low) 1q, 2q 5, 9 true output 1q , 2q 6, 8 complement output gnd 7 ground (0 v) v cc 14 supply voltage table 3. function table [1] input output ns d nr d ncp nd nq nq l hxxhl hl xxl h l l xxhh table 4. function table [1] input output ns d nr d ncp nd nq n+1 nq n+1 hh? llh hh? hhl
74lvc74a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 5 april 2013 5 of 18 nxp semiconductors 74lvc74a-q100 dual d-type flip-flop with set and reset; positive-edge trigger 7. limiting values [1] the minimum input voltage ratings may be excee ded if the input current ratings are observed. [2] the output voltage ratings may be exceeded if the output current ratings are observed. [3] for so14 packages: above 70 ? c the value of p tot derates linearly with 8 mw/k. for tssop14 packages: above 60 ? c the value of p tot derates linearly with 5.5 mw/k. for dhvqfn14 packages: above 60 ? c the value of p tot derates linearly with 4.5 mw/k. 8. recommended operating conditions table 5. limiting values in accordance with the absolute maximum rating system (iec 60134). voltages are referenced to gnd (ground = 0 v). symbol parameter conditions min max unit v cc supply voltage ? 0.5 +6.5 v i ik input clamping current v i < 0 v ? 50 - ma v i input voltage [1] ? 0.5 +6.5 v i ok output clamping current v o > v cc or v o < 0 v - ? 50 ma v o output voltage [2] ? 0.5 v cc + 0.5 v i o output current v o = 0 v to v cc - ? 50 ma i cc supply current - 100 ma i gnd ground current ? 100 - ma t stg storage temperature ? 65 +150 ?c p tot total power dissipation t amb = ? 40 ? c to +125 ?c [3] - 500 mw table 6. recommended operating conditions symbol parameter conditions min typ max unit v cc supply voltage for maximum speed performance 1.65 - 3.6 v for low-voltage applications 1.2 - 3.6 v v i input voltage 0 - 5.5 v v o output voltage 0 - v cc v t amb ambient temperature ? 40 - +125 ?c ? t/ ? v input transition rise and fall rate v cc = 1.65 v to 2.7 v 0 - 20 ns/v v cc = 2.7 v to 3.6 v 0 - 10 ns/v
74lvc74a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 5 april 2013 6 of 18 nxp semiconductors 74lvc74a-q100 dual d-type flip-flop with set and reset; positive-edge trigger 9. static characteristics [1] all typical values are measured at v cc = 3.3 v (unless stated otherwise) and t amb =25 ? c. table 7. static characteristics at recommended operating conditions. volt ages are referenced to gnd (ground = 0 v). symbol parameter conditions ? 40 ? c to +85 ?c ? 40 ? c to +125 ?c unit min typ [1] max min max v ih high-level input voltage v cc = 1.2 v 1.08 - - 1.08 - v v cc = 1.65 v to 1.95 v 0.65 ? v cc - - 0.65 ? v cc -v v cc = 2.3 v to 2.7 v 1.7 - - 1.7 - v v cc = 2.7 v to 3.6 v 2.0 - - 2.0 - v v il low-level input voltage v cc = 1.2 v - - 0.12 - 0.12 v v cc = 1.65 v to 1.95 v - - 0.35 ? v cc -0 . 3 5 ? v cc v v cc = 2.3 v to 2.7 v - - 0.7 - 0.7 v v cc = 2.7 v to 3.6 v - - 0.8 - 0.8 v v oh high-level output voltage v i =v ih or v il i o = ? 100 ? a; v cc =1.65vto3.6v v cc ? 0.2 - - v cc ? 0.3 - v i o = ? 4ma; v cc = 1.65 v 1.2 - - 1.05 - v i o = ? 8ma; v cc = 2.3 v 1.8 - - 1.65 - v i o = ? 12 ma; v cc = 2.7 v 2.2 - - 2.05 - v i o = ? 18 ma; v cc = 3.0 v 2.4 - - 2.25 - v i o = ? 24 ma; v cc = 3.0 v 2.2 - - 2.0 - v v ol low-level output voltage v i =v ih or v il i o = 100 ? a; v cc = 1.65 v to 3.6 v - - 0.2 - 0.3 v i o =4ma; v cc = 1.65 v - - 0.45 - 0.65 v i o =8ma; v cc = 2.3 v - - 0.6 - 0.8 v i o =12ma; v cc = 2.7 v - - 0.4 - 0.6 v i o =24ma; v cc = 3.0 v - - 0.55 - 0.8 v i i input leakage current v cc = 3.6 v; v i =5.5vorgnd - ? 0.1 ? 5- ? 20 ? a i cc supply current v cc = 3.6 v; v i =v cc or gnd; i o =0a -0.110-40 ? a ? i cc additional supply current per input pin; v cc = 2.7 v to 3.6 v; v i =v cc ? 0.6 v; i o =0a - 5 500 - 5000 ? a c i input capacitance v cc = 0 v to 3.6 v; v i =gndtov cc -4 . 0---p f
74lvc74a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 5 april 2013 7 of 18 nxp semiconductors 74lvc74a-q100 dual d-type flip-flop with set and reset; positive-edge trigger 10. dynamic characteristics table 8. dynamic characteristics voltages are referenced to gnd (ground = 0 v). for test circuit see figure 9 . symbol parameter conditions ? 40 ? c to +85 ? c ? 40 ? c to +125 ?c unit min typ [1] max min max t pd propagation delay ncp to nq, nq ; see figure 7 [2] v cc = 1.2 v - 15 - - - ns v cc = 1.65 v to 1.95 v 1.0 5.0 10.3 1.0 11.9 ns v cc = 2.3 v to 2.7 v 1.8 2.9 5.8 1.8 6.7 ns v cc = 2.7 v 1.0 2.7 6.0 1.0 7.5 ns v cc = 3.0 v to 3.6 v 1.0 2.6 5.2 1.0 6.5 ns ns dtonq, nq ; see figure 8 v cc = 1.2 v - 15 - - - ns v cc = 1.65 v to 1.95 v 0.5 4.0 10.6 0.5 12.2 ns v cc = 2.3 v to 2.7 v 1.0 2.4 6.1 1.0 7.1 ns v cc = 2.7 v 1.0 2.9 6.4 1.0 8.0 ns v cc = 3.0 v to 3.6 v 1.0 2.2 5.4 1.0 7.0 ns nr d to nq, nq ; see figure 8 v cc = 1.2 v - 15 - - - ns v cc = 1.65 v to 1.95 v 0.5 4.1 10.7 0.5 12.4 ns v cc = 2.3 v to 2.7 v 1.0 2.4 6.1 1.0 7.1 ns v cc = 2.7 v 1.0 3.0 6.4 1.0 8.0 ns v cc = 3.0 v to 3.6 v 1.0 2.2 5.4 1.0 7.0 ns t w pulse width clock high or low; see figure 7 v cc = 1.65 v to 1.95 v 5.0 - - 5.0 - ns v cc = 2.3 v to 2.7 v 4.0 - - 4.0 - ns v cc = 2.7 v 3.3 - - 4.5 - ns v cc = 3.0 v to 3.6 v 3.3 1.3 - 4.5 - ns set or reset low; see figure 8 v cc = 1.65 v to 1.95 v 5.0 - - 5.0 - ns v cc = 2.3 v to 2.7 v 4.0 - - 4.0 - ns v cc = 2.7 v 3.3 - - 4.5 - ns v cc = 3.0 v to 3.6 v 3.3 1.7 - 4.5 - ns t rec recovery time set or reset; see figure 8 v cc = 1.65 v to 1.95 v 1.5 - - 1.5 - ns v cc = 2.3 v to 2.7 v 1.5 - - 1.5 - ns v cc = 2.7 v 1.5 - - 1.0 - ns v cc = 3.0 v to 3.6 v +1.0 ? 3.0 - 1.0 - ns
74lvc74a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 5 april 2013 8 of 18 nxp semiconductors 74lvc74a-q100 dual d-type flip-flop with set and reset; positive-edge trigger [1] typical values are measured at t amb =25 ? c and v cc = 1.2 v, 1.8 v, 2.5 v, 2.7 v and 3.3 v respectively. [2] t pd is the same as t plh and t phl . [3] skew between any two outputs of the same package switching in the same direction. this parameter is guaranteed by design. [4] c pd is used to determine the dynamic power dissipation (p d in ? w). p d =c pd ? v cc 2 ? f i ? n+ ? (c l ? v cc 2 ? f o ) where: f i = input frequency in mhz; f o = output frequency in mhz c l = output load capacitance in pf v cc = supply voltage in volts n = number of inputs switching ? (c l ? v cc 2 ? f o ) = sum of the outputs t su set-up time nd to ncp; see figure 7 v cc = 1.65 v to 1.95 v 3.0 - - 3.0 - ns v cc = 2.3 v to 2.7 v 2.5 - - 2.5 - ns v cc = 2.7 v 2.2 - - 2.2 - ns v cc = 3.0 v to 3.6 v 2.0 0.8 - 2.0 - ns t h hold time nd to ncp; see figure 7 v cc = 1.65 v to 1.95 v 2.0 - - 2.0 - ns v cc = 2.3 v to 2.7 v 1.5 - - 1.5 - ns v cc = 2.7 v 1.0 - - 1.0 - ns v cc = 3.0 v to 3.6 v +1.0 ? 0.2 - 1.0 - ns f max maximum frequency ncp; see figure 7 v cc = 1.65 v to 1.95 v 100 - - 80 - mhz v cc = 2.3 v to 2.7 v 125 - - 100 - mhz v cc = 2.7 v 150 - - 120 - mhz v cc = 3.0 v to 3.6 v 150 250 - 120 - mhz t sk(o) output skew time v cc = 3.0 v to 3.6 v [3] - - 1.0 - 1.5 ns c pd power dissipation capacitance per flip-flop; v i =gndtov cc [4] v cc = 1.65 v to 1.95 v - 12.4 - - - pf v cc = 2.3 v to 2.7 v - 16.0 - - - pf v cc = 3.0 v to 3.6 v - 19.1 - - - pf table 8. dynamic characteristics ?continued voltages are referenced to gnd (ground = 0 v). for test circuit see figure 9 . symbol parameter conditions ? 40 ? c to +85 ? c ? 40 ? c to +125 ?c unit min typ [1] max min max
74lvc74a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 5 april 2013 9 of 18 nxp semiconductors 74lvc74a-q100 dual d-type flip-flop with set and reset; positive-edge trigger 11. ac waveforms the shaded areas indicate when the input is per mitted to change for predictable output performance. measurement points are given in table 9 . v ol and v oh are typical output voltage levels that occur with the output load. fig 7. clock propagation delays, pulse widths, set-up, hold times and maximum frequency mna422 t h t su t h t phl t phl t w t plh t plh t su 1/f max v m v m v m v m v i gnd v i gnd ncp input nd input v oh v ol nq output v oh v ol nq output
74lvc74a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 5 april 2013 10 of 18 nxp semiconductors 74lvc74a-q100 dual d-type flip-flop with set and reset; positive-edge trigger measurement points are given in table 9 . v ol and v oh are typical output voltage levels that occur with the output load. fig 8. set and reset propagation delays, pulse widths and recovery time mna423 t rec t phl t phl t w t plh t plh v m v m v m t w v m v m v i gnd v i gnd nsd input v i gnd nrd input ncp input v oh v ol nq output v oh v ol nq output table 9. measurement points supply voltage input output v cc v i v m v m 1.2 v v cc 0.5 ? v cc 0.5 ? v cc 1.65 v to 1.95 v v cc 0.5 ? v cc 0.5 ? v cc 2.3 v to 2.7 v v cc 0.5 ? v cc 0.5 ? v cc 2.7 v 2.7 v 1.5 v 1.5 v 3.0 v to 3.6 v 2.7 v 1.5 v 1.5 v
74lvc74a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 5 april 2013 11 of 18 nxp semiconductors 74lvc74a-q100 dual d-type flip-flop with set and reset; positive-edge trigger test data is given in table 10 . definitions for test circuit: r l = load resistance. c l = load capacitance including jig and probe capacitance. r t = termination resistance should be equal to output impedance z o of the pulse generator. fig 9. load circuitry for switching times v m v m t w t w 10 % 90 % 0 v v i v i negative pulse positive pulse 0 v v m v m 90 % 10 % t f t r t r t f 001aaf615 v cc v i v o dut c l r t r l pulse generator table 10. test data supply voltage input load v ext v cc v i t r , t f c l r l t plh , t phl t plz , t pzl t phz , t pzh 1.2 v v cc ? 2 ns 30 pf 1 k ? open 2 ? v cc gnd 1.65 v to 1.95 v v cc ? 2 ns 30 pf 1 k ? open 2 ? v cc gnd 2.3 v to 2.7 v v cc ? 2 ns 30 pf 500 ? open 2 ? v cc gnd 2.7v 2.7v ? 2.5 ns 50 pf 500 ? open 2 ? v cc gnd 3.0vto3.6v 2.7v ? 2.5 ns 50 pf 500 ? open 2 ? v cc gnd
74lvc74a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 5 april 2013 12 of 18 nxp semiconductors 74lvc74a-q100 dual d-type flip-flop with set and reset; positive-edge trigger 12. package outline fig 10. package outline sot108-1 (so14) unit a max. a 1 a 2 a 3 b p cd (1) e (1) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm inches 1.75 0.25 0.10 1.45 1.25 0.25 0.49 0.36 0.25 0.19 8.75 8.55 4.0 3.8 1.27 6.2 5.8 0.7 0.6 0.7 0.3 8 0 o o 0.25 0.1 dimensions (inch dimensions are derived from the original mm dimensions) note 1. plastic or metal protrusions of 0.15 mm (0.006 inch) maximum per side are not included. 1.0 0.4 sot108-1 x w m a a 1 a 2 b p d h e l p q detail x e z e c l v m a (a ) 3 a 7 8 1 14 y 076e06 ms-012 pin 1 index 0.069 0.010 0.004 0.057 0.049 0.01 0.019 0.014 0.0100 0.0075 0.35 0.34 0.16 0.15 0.05 1.05 0.041 0.244 0.228 0.028 0.024 0.028 0.012 0.01 0.25 0.01 0.004 0.039 0.016 99-12-27 03-02-19 0 2.5 5 mm scale so14: plastic small outline package; 14 leads; body width 3.9 mm sot108-1
74lvc74a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 5 april 2013 13 of 18 nxp semiconductors 74lvc74a-q100 dual d-type flip-flop with set and reset; positive-edge trigger fig 11. package outline sot402-1 (tssop14) unit a 1 a 2 a 3 b p cd (1) e (2) (1) eh e ll p qz ywv references outline version european projection issue date iec jedec jeita mm 0.15 0.05 0.95 0.80 0.30 0.19 0.2 0.1 5.1 4.9 4.5 4.3 0.65 6.6 6.2 0.4 0.3 0.72 0.38 8 0 o o 0.13 0.1 0.2 1 dimensions (mm are the original dimensions) notes 1. plastic or metal protrusions of 0.15 mm maximum per side are not included. 2. plastic interlead protrusions of 0.25 mm maximum per side are not included. 0.75 0.50 sot402-1 mo-153 99-12-27 03-02-18 w m b p d z e 0.25 17 14 8 a a 1 a 2 l p q detail x l (a ) 3 h e e c v m a x a y 0 2.5 5 mm scale tssop14: plastic thin shrink small outline package; 14 leads; body width 4.4 mm sot402-1 a max. 1.1 pin 1 index
74lvc74a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 5 april 2013 14 of 18 nxp semiconductors 74lvc74a-q100 dual d-type flip-flop with set and reset; positive-edge trigger fig 12. package outline sot762-1 (dhvqfn14) terminal 1 index area 0.5 1 a 1 e h b unit y e 0.2 c references outline version european projection issue date iec jedec jeita mm 3.1 2.9 d h 1.65 1.35 y 1 2.6 2.4 1.15 0.85 e 1 2 0.30 0.18 0.05 0.00 0.05 0.1 dimensions (mm are the original dimensions) sot762-1 mo-241 - - - - - - 0.5 0.3 l 0.1 v 0.05 w 0 2.5 5 mm scale sot762-1 dhvqfn14: plastic dual in-line compatible thermal enhanced very thin quad flat package; no leads; 14 terminals; body 2.5 x 3 x 0.85 mm a (1) max. a a 1 c detail x y y 1 c e l e h d h e e 1 b 26 13 9 8 7 1 14 x d e c b a 02-10-17 03-01-27 terminal 1 index area ac c b v m w m e (1) note 1. plastic or metal protrusions of 0.075 mm maximum per side are not included. d (1)
74lvc74a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 5 april 2013 15 of 18 nxp semiconductors 74lvc74a-q100 dual d-type flip-flop with set and reset; positive-edge trigger 13. abbreviations 14. revision history table 11. abbreviations acronym description cdm charged device model dut device under test esd electrostatic discharge hbm human body model mm machine model mil military ttl transistor-transistor logic table 12. revision history document id release date data sheet status change notice supersedes 74lvc74a_q100 v.2 20130405 product data sheet - 74lvc74a_q100 v.1 modifications: ? section 2 ? features and benefits ? removed redundant temperature range 74lvc74a_q100 v.1 20130326 product data sheet - -
74lvc74a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 5 april 2013 16 of 18 nxp semiconductors 74lvc74a-q100 dual d-type flip-flop with set and reset; positive-edge trigger 15. legal information 15.1 data sheet status [1] please consult the most recently issued document before initiating or completing a design. [2] the term ?short data sheet? is explained in section ?definitions?. [3] the product status of device(s) described in this document may have changed since this document was published and may differ in case of multiple device s. the latest product status information is available on the internet at url http://www.nxp.com . 15.2 definitions draft ? the document is a draft versi on only. the content is still under internal review and subject to formal approval, which may result in modifications or additions. nxp semiconductors does not give any representations or warranties as to the accuracy or completeness of information included herein and shall hav e no liability for the consequences of use of such information. short data sheet ? a short data sheet is an extract from a full data sheet with the same product type number(s) and title. a short data sheet is intended for quick reference only and should not be relied upon to contain detailed and full information. for detailed and full information see the relevant full data sheet, which is available on request vi a the local nxp semiconductors sales office. in case of any inconsistency or conflict with the short data sheet, the full data sheet shall prevail. product specification ? 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stress above one or more limiting values (as defined in the absolute maximum ratings system of iec 60134) will cause permanent damage to the device. limiting values are stress ratings only and (proper) operation of the device at these or any other conditions above those given in the recommended operating conditions section (if present) or the characteristics sections of this document is not warranted. constant or repeated exposure to limiting values will permanently and irreversibly affect the quality and reliability of the device. terms and conditions of commercial sale ? nxp semiconductors products are sold subject to the gener al terms and conditions of commercial sale, as published at http://www.nxp.com/profile/terms , unless otherwise agreed in a valid written individual agreement. in case an individual agreement is concluded only the terms and conditions of the respective agreement shall apply. nxp semiconductors hereby expressly objects to applying the customer?s general terms and conditions with regard to the purchase of nxp semiconducto rs products by customer. document status [1] [2] product status [3] definition objective [short] data sheet development this document contains data from the objecti ve specification for product development. preliminary [short] data sheet qualification this document contains data from the preliminary specification. product [short] data sheet production this document contains the product specification.
74lvc74a_q100 all information provided in this document is subject to legal disclaimers. ? nxp b.v. 2013. all rights reserved. product data sheet rev. 2 ? 5 april 2013 17 of 18 nxp semiconductors 74lvc74a-q100 dual d-type flip-flop with set and reset; positive-edge trigger no offer to sell or license ? nothing in this document may be interpreted or construed as an offer to sell products t hat is open for acceptance or the grant, conveyance or implication of any licens e under any copyrights, patents or other industrial or intellectual property rights. export control ? this document as well as the item(s) described herein may be subject to export control regu lations. export might require a prior authorization from competent authorities. translations ? a non-english (translated) version of a document is for reference only. the english version shall prevail in case of any discrepancy between the translated and english versions. 15.4 trademarks notice: all referenced brands, produc t names, service names and trademarks are the property of their respective owners. 16. contact information for more information, please visit: http://www.nxp.com for sales office addresses, please send an email to: salesaddresses@nxp.com
nxp semiconductors 74lvc74a-q100 dual d-type flip-flop with set and reset; positive-edge trigger ? nxp b.v. 2013. all rights reserved. for more information, please visit: http://www.nxp.com for sales office addresses, please se nd an email to: salesaddresses@nxp.com date of release: 5 april 2013 document identifier: 74lvc74a_q100 please be aware that important notices concerning this document and the product(s) described herein, have been included in section ?legal information?. 17. contents 1 general description . . . . . . . . . . . . . . . . . . . . . . 1 2 features and benefits . . . . . . . . . . . . . . . . . . . . 1 3 ordering information . . . . . . . . . . . . . . . . . . . . . 2 4 functional diagram . . . . . . . . . . . . . . . . . . . . . . 2 5 pinning information . . . . . . . . . . . . . . . . . . . . . . 3 5.1 pinning . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 3 5.2 pin description . . . . . . . . . . . . . . . . . . . . . . . . . 4 6 functional description . . . . . . . . . . . . . . . . . . . 4 7 limiting values. . . . . . . . . . . . . . . . . . . . . . . . . . 5 8 recommended operating conditions. . . . . . . . 5 9 static characteristics. . . . . . . . . . . . . . . . . . . . . 6 10 dynamic characteristics . . . . . . . . . . . . . . . . . . 7 11 ac waveforms . . . . . . . . . . . . . . . . . . . . . . . . . . 9 12 package outline . . . . . . . . . . . . . . . . . . . . . . . . 12 13 abbreviations . . . . . . . . . . . . . . . . . . . . . . . . . . 15 14 revision history . . . . . . . . . . . . . . . . . . . . . . . . 15 15 legal information. . . . . . . . . . . . . . . . . . . . . . . 16 15.1 data sheet status . . . . . . . . . . . . . . . . . . . . . . 16 15.2 definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 15.3 disclaimers . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 15.4 trademarks. . . . . . . . . . . . . . . . . . . . . . . . . . . 17 16 contact information. . . . . . . . . . . . . . . . . . . . . 17 17 contents . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18

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